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I promise I'm not turning this into a spam blog for my business (see the business twitter account for all my self-promotion), but I want to get the word out about early-adopter discount codes that I have made available.  I'll start an MSD specific blog and continue promoting things there as well. The discount code is for $99 off, which is a free Self-support subscription.  There are only 20 purchases available with this code: a5b2758959 Please give it a try, download and install the product, go through the Hello World tutorial , let me know how it all works. Thank you!

I have been working with commercial EDA tools (Verilog, VHDL, etc.) for years and always found them to be quite overpriced and frustrating.  Whenever I bring up the idea of using open source tools I get responses just like I got when first brining up Linux in the workplace back in 2001.  Things like, "you get what you pay for" and "it's only free if you don't value your time."  Red Hat (and SUSE/Novell) addressed those concerns for business people and made Linux mainstream (and put UNIX out of business and made a lot money for themselves in the process).  Maybe a similar business could do the same for open source EDA. To that end, I have quit my job and I've spent the past few week putting this business together.  What do you think? https://millenniumsoftwaredesign.com (AKA, https://msd.llc/ )

I just took a quick look at svlib from Verilab.  Very cool.  It's a library for SystemVerilog that gives you file globbing, regular expressions, a better string class, simple ini config file parsing (with yaml support promised for the future!), and more.  It was announced back in March and it took me this long to getting around to reading about it.  Hopefully it doesn't take me that long to actually try it out :-) They welcome feedback so brace yourself, here it comes.  First of all it's open source (Apache license) which is excellent.  It's open source and it has documentation.  Amazing!  :-)  It is not currently developed openly though.  Could we get a github, bitbucket, or sourceforge project going?  Our industry (design verification) desperately needs to admit and recognize that we are software developers.  I mean no, we are verifiers!  Bug finders!  It just so happens that writing software is the primary tech...

At the end of my last post I promised I would have another non-determinism (AKA, race condition) example from recent real-life experience. Here it comes. Before I show you any code I want to explain how this race condition was introduced. We had a signal in an interface that needed to be widened. We had a function in some simulation-only code that looked at part of that signal and didn't care about the new bits that were added. The engineer who widened the signal decided not to change the function and instead added a new variable and assigned (using the assign keyword) the bits of interest from the newly widened signal to this new variable. He then passed this new variable to the original function in place of the original newly-widened one. Seems reasonable, right? Well, after he made that change some tests started failing and after some digging it began to look like a race condition, but it wasn't obvious where the race was coming from. The problem was that assign s...

In my last post we looked at some example code that showed off Verilog's non-determinism. Here it is again (you can actually run it on multiple simulators here on EDA Playground ): module top; reg ready; integer result; initial begin #10; ready <= 1; result <= 5; end initial begin @(posedge ready); if(result == 5) begin $display("result was ready"); end else begin $display("result was not ready"); end end endmodule Just to review from last time, the problem is that sometimes the @(posedge ready) will trigger before result has the value 5 and sometimes it will trigger after result has the value 5. We have called this non-determinism but a more common term for it is, race condition. There is a race between the values of ready and result making it to that second process (the second initial block). If result is updated first (wins the race) then everything runs as...

A series of blog posts by Jan Decaluwe criticize Verilog for being "non-deterministic" and therefore fundamentally broken. This one has a code example that illustrates the fact. During a lively Twitter conversation about it I fleshed out the example and put it on EDA Playground so we could all view it and, even better, run it with all the simulators that EDA Playground provides and see what actually happens. Click here to see and run the example code yourself. If you run the example you'll see that it behaves the same for all the simulators available on EDA Playground, except one. Jan explains that they are all compliant with the Verilog specification because the specification allows for either behavior. Jan expertly explains in this post how that can be. Despite these clear examples and explanations I'm left with the feeling of, why should I care? Apparently a lot of other users of the Verilog language have the same feeling as me. I tried to see Jan's ...

Being a relatively early adopter of svunit (for unit testing SystemVerilog code), I had a fair amount of code written to work with the early 0.X versions of svunit. The maintainers of svunit have made some good progress and are now on version 2.3 (as of writing this). My old tests don't work with the new version of the framework, but I figured out how to update them. Just in case anyone else is in the same predicament, I will share the steps I took to fix things: In the *_unit_test.sv file: remove typedef class c_<UUT>_unit_test keep the module <UUT>_unit_test declaration, but delete everything in the module except for the string name… and any interface declarations you may have added delete the c_<UUT>_unit_test class declaration add svunit_testcase svunit_ut; under the string name… Now that this is a module and not a class, tasks and functions declared in here might need to have the automatic keyword added to the declaration in order to beh...

I found another one (I guess I still need to order that book ). In using the UVM, I have some sequences randomizing other sub sequences. I really want it to work like this (simplified, non-UVM) example: class Foo; rand int bar; function void display (); $display ( "bar: %0d" , bar); endfunction endclass class Bar; int bar; function void body (); Foo foo = new (); bar = 3; foo. display (); assert (foo. randomize () with {bar == this .bar;}); foo. display (); endfunction endclass module top; Bar bar; initial begin bar = new (); bar. body (); end endmodule See the problem there? Here's what prints out when you run the above: bar: 0 bar: -1647275392 foo.bar is not constrained to be 3 like you might expect. That's because this.bar refers to bar that is a member of class Foo, not bar that's a member of class Bar. As far as I can tell, there is no way to refer to ba...

At DVCon 2013 I asked JL Gray 's panel if we would ever have Free tools, like the software world. None of panelists seemed to think so, one of the panelists, a Mentor employee, scoffed, "you get what you pay for with free tools." Never mind that their (and Cadence's and Synopsys's) products are very likely developed with tools that contain millions of lines of Free software. So, to work towards answering my own question, I spent a little time and looked for Free/Open Source verilog simulators. Here's what I found: Icarus Verilog GPL Cver PVSim Verilog Simulator VeriWell Verilog Simulator I have personally used Icarus and Cver before, but not very extensively.  They were usable and seemed pretty complete, for Verilog.  None of the above claim any support of SystemVerilog except for Icarus.  The Icarus developer at one point expressed abhorrence at SystemVerilog but it seems support for some parts of the language have been added. PVSim and Veri...

I just ran into another fun SystemVerilog Gotcha. Look this code over and see what you think should happen: module top; string foo[ byte ]; byte bar; initial begin $display ( "%0d" , "a string" == foo[ "not a byte" ]); foo[ "e" ] = "a string" ; $display ( "%0d" , "a string" == foo[ "not a byte" ]); bar = "not a byte" ; $display ( "bar: %0s" , bar); end endmodule Compile error, right? You can't index into an associative array with a string when it is declared to take a byte, can you? And you can't assign a string to a variable of type byte, right? Ha! This actually compiles and runs without any errors or warnings. String literals are packed arrays of bytes and they are automatically truncated to the width of the thing they are being assigned to. Here's the output from running the above code: 0 1 bar: e After my last...

This is a long post with a lot of SystemVerilog code. The purpose of this entry is to hopefully save you from beating your head against the wall trying to figure out some of the subtleties of SystemVerilog processes (basically, threads). Subtleties like these are commonly referred to in the industry as "Gotchas" which makes them sound so playful and fun, but they really aren't either. I encourage you to run these examples with your simulator (if you have access to one) so that a) you can see the results first hand and better internalize what's going on, and b) you can tell me in the comments if this code works fine for you and I'll know I should go complain to my simulator vendor. OK, I'll start with a warm-up that everyone who writes any Verilog or SystemVerilog at all should be aware of, tasks are static by default. If you do this: module top; task do_stuff ( int wait_time); #wait_time $display ( "waited %0d, then did stuff" , wa...

I started out trying to write an eloquent essay on the merits of different ways of sharing new ideas and information in order to further the art of digital design verification (in other words, how to market this stuff), but I couldn't make it sound right. Instead, let me just point to some recent examples: Good examples Namespaces, Build Order, and Chickens Cadence's UVM video series These are brief and to-the-point. If you have a question, they quickly give you answer. If you are taking 2 or 3 minutes to browse the internet while waiting for a simulation to finish, maybe even on your phone while you take a little time away from your desk, you can get all the info in that time. Perfect. Examples of Ideas That Could be Marketed Better Monitoring signals by name, for the UVM register package and more and: A 30 Minute Project Makeover Using Continuous Integration First of all, kudos to Verilab for sharing ideas, knowledge, and source code as much they do. The...

This whole virtualenv thing is pretty cool, but it has always seemed too specific to Python for me. Let me see if I can explain. At first I had no use for virtualenv whatsoever, I could just sudo apt-get install python-whatever and get what I needed. As my distro got older and I didn't want to update my whole system, I started using virtualenv and pip to install and manage python packages instead of apt. It's great, except that the postgresql packages that came with my distro were getting crusty too. Because postgresql is not a python package, I get no help from virtualenv. Does anyone else have this problem? How do you deal with it? This reminds me of a very old problem from the chip design (EDA, ASIC design, whatever you want to call it) world. To design chips you buy licenses for expensive simulators and synthesis tools, and those tools are constantly being revved, fixing old bugs, introducing new features, and unfortunately, introducing new bugs. Because of that...

I have written A UNIX/Linux environment manager that allows on-the-fly configuration of your shell environment. It's called, albion . Using albion, environment variables, aliases, functions, and so forth can be changed without requiring you to do the tedious log-out-and-log-back-in-again routine. Simply type 'albion load ' and your shell environment will be reconfigured according to the specification in your environment file. It should work with any POSIXy shell (bash, ksh, zsh, etc.) Albion is similar to the Environment Modules Project , however, environment configuration files (configs) are written in standard shell language, not tcl. Another improvement over modules is that when unloaded, the effect of the configs is correctly undone, even if the configs have changed or been deleted after loading. The main albion tool is written in Python, with some supporting pieces written in POSIX shell code. albion is currently alpha quality. The core functionality seems to be ...

I stumbled onto a new build tool today: fabricate . I can't believe how cool it is, and that nobody has thought of it before (OK, actually, one person did , but still!). You give it a command, and it runs the command with strace and looks for all the files the command reads and produces and uses those as the command's dependencies and outputs, respectively. The next time you run the command with fabricate, if the outputs don't exist or the dependencies have changed it re-runs the command, otherwise, it doesn't. In other words, it does all the work that you normally would try and do with make, automatically. Another cool thing about this is that it will work with anything. You don't have to write builders for it like you would for scons (another tool I looked at for a bit). I spent some time trying to get scons to run modelsim compiles and simulations for me, and it was way too hard to make it work. I just tried fabricate with a small modelsim job and it ...

A friend of mine who is also a verification engineer lamented to me that Cadence didn't seem to be supporting SystemVerilog very well. This is what fell out of my head and into the email reply I sent him. I notice that Cadence bloggers seem to all like specmen E better than systemverilog, and synopsys people, of course, like VMM more than anything else. So, I guess I’m not surprised that Cadence isn’t supporting SystemVerilog that well. The EDA industry is weird. I like how the software world, with open source, collaborates so well on developing the best tools for everyone. There almost needs to be a Linux-like simulator that everyone in EDA rallies around and works together on. Or if Linux isn’t the best comparison, maybe gcc, or firefox, or apache. They are defacto standard tools now in the software world. In the software world, if you have a new compiled language, you pretty much have to write a gcc (Gnu Compiler Collection) compiler for it. If you have a...