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Showing posts from June, 2022

My 2013 DVCon Paper and Poster

I just noticed that my 2013 DVCon paper and poster are no longer archived on the DVCon website.  So, for my records at least, here they are: The poster:  Poster: ASIC-Strength Verification in a Fast-Moving FPGA World The paper:  ASIC-Strength Verification in a Fast-Moving FPGA World Apologies for the PDF of the paper, but converting it to html requires more time than I have at the moment.