SystemVerilog String Literal "Gotcha"

I just ran into another fun SystemVerilog Gotcha. Look this code over and see what you think should happen:

module top;
   string foo[byte];
   byte bar;
   initial begin 
      $display("%0d", "a string" == foo["not a byte"]);
      foo["e"] = "a string";
      $display("%0d", "a string" == foo["not a byte"]);
      bar = "not a byte";
      $display("bar: %0s", bar);
   end 
endmodule

Compile error, right? You can't index into an associative array with a string when it is declared to take a byte, can you? And you can't assign a string to a variable of type byte, right?

Ha! This actually compiles and runs without any errors or warnings. String literals are packed arrays of bytes and they are automatically truncated to the width of the thing they are being assigned to. Here's the output from running the above code:

0
1
bar: e

After my last blog post I was informed that there's a book that has 101 SystemVerilog Gotchas in it. I didn't believe it, but I think I'm starting to see how it could be possible.

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