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We all know that in the world of general software Open Source has all but won. Linux is everywhere. Nearly all programming languages are Open Source (meaning their compilers/interpreters). IDE's, build tools, revision control, syntax highlighters, refactoring tools, you name it, if it's a development tool it's Open Source. Major infrastructure is Open Source too. I mentioned the Linux operating system, but all the major applications are Open Source too: web servers, databases, queueing systems, messaging systems, load balancing, caching systems, GUI frameworks, encryption, authentication, email servers, instant messaging servers, blog engines, you name it. In the world of Electronic Design Automation (EDA), Open Source has not won. We do now develop on Linux and we use a lot of ancillary tools from the software world that are Open Source such as scripting languages, text editors, databases, web frameworks, build systems, and so forth, but our core tools are still very mu...

Stripe announced bitcoin support .  There has been much discussion on hacker news about it .  Lots of people are not seeing the benefits of bitcoin over credit cards for individual shoppers. They talk about the fraud protection that credit cards provide them as customers and the 1% or whatever cash back they get on each purchase from the credit card companies that they would be giving up.  I don't think they fully understand the trade-offs here. First of all, the cash back.  Credit card companies are charging merchants a percentage of each transaction larger than the 1% whatever they are giving you back (how else do they stay in business?).  What people may be forgetting is that retailers are not just eating that percentage cost that the credit cards are charging them.  They are most definitely passing that cost on to all of us consumers in the form of higher prices.  If enough transactions happened with bitcoin that would lower prices for all of us....

Last year I started assembling a little garage gym so I could do some weight lifting in the comfort of home. I scoured the online classifieds and found good deals on used power racks, a bench, and some weights. I was doing pretty well finding these deals, I thought. The one oddity was with the weights. The seller wouldn't sell them separate from this monster: I had no use for this because I had bought into the idea that compound lifts were the best and this enormous and heavy thing served only to isolate your shoulders. I took it anyway because the guy was nice and he was giving me a good deal on the weights whether this was included or not. I was also thinking in the back of my head that I have a friend that likes metalworking that could probably help me turn it into something more useful. Nearly a full year later my hope was finally realized. I stored it as is in my garage for about 6 months. My basement was being remodeled so there were lots of things in the garage...

In my previous post I promised I would write about more interesting cases of streaming using a slice_size and arrays of ints and bytes.  Well, I just posted another set of streaming examples to edaplayground .  I'm going to mostly let you look at that code and learn by example, but I will take some time in this post to explain what I think is the trickiest of the conversions.  When you go to edaplayground, choose the Modelsim simulator to run these.  Riviera-PRO is currently the only other SystemVerilog simulator choice on edaplayground, and it messes up on the tricky ones (more on that in a bit). These examples demonstrate using the streaming operator to do these conversions: unpacked array of bytes to int queue of ints to queue of bytes queue of bytes to queue of ints int to queue of bytes class to queue of bytes Of all those examples, the queue of ints to queue of bytes and the queue of bytes to queue of ints are the tricky ones that I want to spend more ...

SystemVerilog has this cool feature that is very handy for converting one type of collection of bits into another type of collection of bits.  It's the streaming operator.  Or the streaming concatenation operator.  Or maybe it's the concatenation of streaming expressions (it's also called pack/unpack parenthetically).  Whatever you want to call it, it's nice.  If you have an array of bytes and you want to turn it into an int, or an array of ints that you want to turn into an array of bytes, or if you have a class instance that you want to turn into a stream of bits, then streaming is amazing.  What used to require a mess of nested for-loops can now be done with a concise single line of code. As nice as it is, getting the hang of the streaming operator is tough.  The SystemVerilog 1800-2012 LRM isn't totally clear (at least to me) on the details of how they work.  The statement from the LRM that really got me was this, "The stream_operator <...

I just took a quick look at svlib from Verilab.  Very cool.  It's a library for SystemVerilog that gives you file globbing, regular expressions, a better string class, simple ini config file parsing (with yaml support promised for the future!), and more.  It was announced back in March and it took me this long to getting around to reading about it.  Hopefully it doesn't take me that long to actually try it out :-) They welcome feedback so brace yourself, here it comes.  First of all it's open source (Apache license) which is excellent.  It's open source and it has documentation.  Amazing!  :-)  It is not currently developed openly though.  Could we get a github, bitbucket, or sourceforge project going?  Our industry (design verification) desperately needs to admit and recognize that we are software developers.  I mean no, we are verifiers!  Bug finders!  It just so happens that writing software is the primary tech...

At the end of my last post I promised I would have another non-determinism (AKA, race condition) example from recent real-life experience. Here it comes. Before I show you any code I want to explain how this race condition was introduced. We had a signal in an interface that needed to be widened. We had a function in some simulation-only code that looked at part of that signal and didn't care about the new bits that were added. The engineer who widened the signal decided not to change the function and instead added a new variable and assigned (using the assign keyword) the bits of interest from the newly widened signal to this new variable. He then passed this new variable to the original function in place of the original newly-widened one. Seems reasonable, right? Well, after he made that change some tests started failing and after some digging it began to look like a race condition, but it wasn't obvious where the race was coming from. The problem was that assign s...