Not Leaky, Just Wrong

Intel recently announced new tools for FPGA design. I should probably try to understand OpenCL better before bagging on it, but when I read, "[OpenCL] allows users to abstract away hardware-specific development and use a higher-level software development flow." I cringe. I don't think that's how we get to a productive, higher-level of abstraction in FPGA design. When you look at the progress of software from low-level detailed design to high-level abstract design you see assembly to C to Java to Python (to pick one line of progression among many). The thing that happened every time a new higher-level language gained traction is people recognized patterns that developers were using over and over in one language and made language features in a new language that made those patterns one-liners to implement.

Examples of design patterns turning into language features are, in assembly people developed the patterns of function calls: push arguments onto the stack, save the program counter, jump to the code the implements the function, the function code pops arguments off the stack, does it's thing, then jumps back to the the code that called it. In C the tedium of all that was abstracted away by the language providing you with syntax to define a function, pass it arguments, and just call return at the end. In C people then started developing patterns of structs containing data and function pointers for operating on that data which turned into classes and objects in Java. Java also abstracted away memory management with a garbage collector. Patterns in Java (Visitor, State, etc.) are no longer needed in Python because of features in that language (related discussion here).

This is the path that makes most sense to me for logic design as well. Right now in RTL Verilog people use patterns like registers (always block that activates on posedge clk, has reset, inputs, outputs, etc.), state machines (case statement and state registers, next_state logic...), interfaces (SV actually attempted to add syntax for this), and so on. It seems like the next step in raising the abstraction level is to have a language with those sorts of constructs built-in. Then let people use that for a while and see what new patterns develop and encapsulate those patterns in new language features. Maybe OpenCL does this? I kind of doubt it if it's a "software development flow." It's probably still abstracting away CPU instructions.


Unknown said…

Maybe for a tiny subset of the FPGA for example a math datapath.
In the grand scheme of FPGA design this is a very small % of the job.
For some reason the EDA vendors seem to believe this is big, or that it is going to be big soon.

Verification on the other hand is huge. Getting the organization to buy into verification as about 50% of the job is still a tough sell.

Full OO verification using SV is still a frontier at many organizations that develop FPGA. The whole OO design style comes more from software and the FPGA teams come from hardware. Getting the FPGA team to embrace OO verification using SV and all the related stuff (assertions, random, coverage) in tough. Let alone climb the mountain which is UVM.

Seems like the industry is a a point where we need to get better at using the tools we have now.
Unknown said…
Another possibility for productivity increase getting better at IP design,use, storage and maintenance. The vendors have proprietary AXI based block diagram tools which design centers can use, however that involves getting wrapped up with the vendors quirks and bugs. In this workflow the team can spend most of their design effort on weird block editor issues, writing wrappers for unexpected cases, and upgrading block diagrams from one version of the tool to the next.

Seems like what is needed here is an open source block diagram tool which just works for design capture (like VI or Emacs is to an RTL design). Then vendors can publish AXI IP to pop down structurally, and just hook up the AXI busses. Such a tool would have to be pretty thin in that you don't want too much magic during the design process in the way of auto generate or auto-connect or other things than can go wrong.
Unknown said…
I like your way of thinking and completely agree on patterns are to circumvent language flaws!

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