At DVCon 2013 I asked JL Gray's panel if we would ever have Free tools, like the software world. None of panelists seemed to think so, one of the panelists, a Mentor employee, scoffed, "you get what you pay for with free tools." Never mind that their (and Cadence's and Synopsys's) products are very likely developed with tools that contain millions of lines of Free software.
So, to work towards answering my own question, I spent a little time and looked for Free/Open Source verilog simulators. Here's what I found:
PVSim Verilog Simulator
VeriWell Verilog Simulator
I have personally used Icarus and Cver before, but not very extensively. They were usable and seemed pretty complete, for Verilog. None of the above claim any support of SystemVerilog except for Icarus. The Icarus developer at one point expressed abhorrence at SystemVerilog but it seems support for some parts of the language have been added.
PVSim and VeriWell were new to me. I'll give them a try, hopefully soon, and post more information.
Another one that should be mentioned is Verilator. I have downloaded and played with this one too. It only supports synthesizable Verilog, so have fun writting a testbench. I think the intent is for you to write your testbench in C++, so if you like that idea than this could be a good one to try too.
Did I miss any?
UPDATE: All of these (except Verilator) plus a host of other free EDA tools are available to easily try out at EDA Playground. Go there now, it's a fun place to play.