I have a new job! I am now a verification engineer at a relatively new hardware company in Utah. I worked on digital design and verification stuff back during internships in college and then for the first few years that I worked full-time. Then about five years ago I switched over to embedded software. It's fun to be back in the hardware design world. Better verification and system modelling was a hot topic five years ago, and it looks like a lot of progress has been made in the intervening years. It's really cool to see. Another big win with the new job is, no more windoze! ASIC designers know a good development environment runs on Linux ;-)
I mostly use this blog to write down helpful reminders for myself, and as a start, here's my first verilog tip. Code browsing with ctags works for verilog too! I used find to get a list of all our verilog files and put that in a file called, file-list.txt. Then I generated tags like so:
ctags -e --verbose --language-force=verilog -L file.list
One huge oversight of emacs verilog-mode is that they overrode the pop-tag-mark keybinding to insert a multi-line comment instead. I got distracted with other things so I haven't done it yet, but I'm sure that's not too hard to fix.
Anyway, I'm excited for the new opportunity. In closing, here are some verification blogs that I found, but haven't read much of. Yet.
How's that for a focused blog post?