A Quick Look at svlib
I just took a quick look at svlib from Verilab. Very cool. It's a library for SystemVerilog that gives you file globbing, regular expressions, a better string class, simple ini config file parsing (with yaml support promised for the future!), and more. It was announced back in March and it took me this long to getting around to reading about it. Hopefully it doesn't take me that long to actually try it out :-) They welcome feedback so brace yourself, here it comes. First of all it's open source (Apache license) which is excellent. It's open source and it has documentation. Amazing! :-) It is not currently developed openly though. Could we get a github, bitbucket, or sourceforge project going? Our industry (design verification) desperately needs to admit and recognize that we are software developers. I mean no, we are verifiers! Bug finders! It just so happens that writing software is the primary tech...