tag:blogger.com,1999:blog-3669809752172683097.post7124628488925488082..comments2024-02-08T04:04:28.385-08:00Comments on Cyclopedia Square: Avoiding Verilog's Non-determinism, Part 2Bryanhttp://www.blogger.com/profile/11394436715172971234noreply@blogger.comBlogger4125tag:blogger.com,1999:blog-3669809752172683097.post-35468918236745103532014-03-03T22:57:39.116-08:002014-03-03T22:57:39.116-08:00Saying that the VHDL is equivalent is wrong and mi...Saying that the VHDL is equivalent is wrong and misses the crucial point: VHDL guarantees the delta cycle but Verilog does not.<br /><br />With a different simulator, the original modified test bench might not have failed. The code would have become fragile, but no one would know yet.Jan Decaluwehttps://www.blogger.com/profile/09718812675859251506noreply@blogger.comtag:blogger.com,1999:blog-3669809752172683097.post-84731308907636703452014-03-01T20:18:37.153-08:002014-03-01T20:18:37.153-08:00Paul, here's the link to your EDA Playground v...Paul, here's the link to your EDA Playground version of the VHDL code (which is formatted nicely):<br /><br />http://www.edaplayground.com/x/3ak<br /><br />Thanks for putting that together.Bryanhttps://www.blogger.com/profile/11394436715172971234noreply@blogger.comtag:blogger.com,1999:blog-3669809752172683097.post-82726034366720510902014-02-28T04:17:23.226-08:002014-02-28T04:17:23.226-08:00Sorry, I don't know how to format the code to ...Sorry, I don't know how to format the code to preserve the indentation - I couldn't use the < pr e> or < code > tags.<br /><br />Paul.Anonymousnoreply@blogger.comtag:blogger.com,1999:blog-3669809752172683097.post-58157227815929368302014-02-28T04:12:48.783-08:002014-02-28T04:12:48.783-08:00This is not a race condition, it's just an exa...This is not a race condition, it's just an example of poor coding where you have different path delays.<br /><br />Here's the equivalent in VHDL and note that I only use signal assignments:<br /><br />use std.textio.all;<br />entity top is<br />end entity;<br />architecture behave of top is<br /> signal foo: bit_vector(3 downto 0);<br /> signal foo_0: bit;<br /> signal ready: bit;<br /><br />begin<br /> -- equivalent of assign<br /> foo_0 <= foo(0);<br /><br /> initial1: process<br /> begin<br /> wait for 10 ns;<br /> foo <= (others=>'0');<br /> ready <= '0';<br /> wait for 10 ns;<br /> foo <= (others=>'1');<br /> ready <= '1';<br /> wait for 10 ns;<br /> foo <= (others=>'0');<br /> ready <= '0';<br /> wait;<br /> end process initial1;<br /><br /> initial2: process(ready)<br /> variable L: line;<br /> begin<br /> write(L, string'("foo[0]:"));<br /> write(L, foo(0));<br /> write(L, string'(" foo_0:"));<br /> write(L, foo_0);<br /> writeline(OUTPUT,L);<br /> write(L, string'(" -----------"));<br /> writeline(OUTPUT,L);<br /> end process initial2;<br />end behave;<br /><br />Here's the output from questa:<br /><br /># Loading std.standard<br /># Loading std.textio(body)<br /># Loading work.top(behave)#1<br />VSIM 1> run -a<br /># foo[0]:0 foo_0:0<br /># -----------<br /># foo[0]:1 foo_0:0<br /># -----------<br /># foo[0]:0 foo_0:1<br /># -----------<br /><br />Paul.Anonymousnoreply@blogger.com