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Showing posts from March, 2013

Free Verilog Simulators

At DVCon 2013 I asked JL Gray 's panel if we would ever have Free tools, like the software world. None of panelists seemed to think so, one of the panelists, a Mentor employee, scoffed, "you get what you pay for with free tools." Never mind that their (and Cadence's and Synopsys's) products are very likely developed with tools that contain millions of lines of Free software. So, to work towards answering my own question, I spent a little time and looked for Free/Open Source verilog simulators. Here's what I found: Icarus Verilog GPL Cver PVSim Verilog Simulator VeriWell Verilog Simulator I have personally used Icarus and Cver before, but not very extensively.  They were usable and seemed pretty complete, for Verilog.  None of the above claim any support of SystemVerilog except for Icarus.  The Icarus developer at one point expressed abhorrence at SystemVerilog but it seems support for some parts of the language have been added. PVSim and Veri