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Showing posts from December, 2009

Open Source EDA Dream

A friend of mine who is also a verification engineer lamented to me that Cadence didn't seem to be supporting SystemVerilog very well. This is what fell out of my head and into the email reply I sent him. I notice that Cadence bloggers seem to all like specmen E better than systemverilog, and synopsys people, of course, like VMM more than anything else. So, I guess I’m not surprised that Cadence isn’t supporting SystemVerilog that well. The EDA industry is weird. I like how the software world, with open source, collaborates so well on developing the best tools for everyone. There almost needs to be a Linux-like simulator that everyone in EDA rallies around and works together on. Or if Linux isn’t the best comparison, maybe gcc, or firefox, or apache. They are defacto standard tools now in the software world. In the software world, if you have a new compiled language, you pretty much have to write a gcc (Gnu Compiler Collection) compiler for it. If you have an idea for a